The present invention relates generally to a memory device and, more particularly, to a semiconductor memory device and method for preventing dummy cells coupled to dummy word lines from over-erasing.
A memory device conventionally may include a transistor that serves as a memory cell coupled to a word line and a bit line. Multiple memory cells may form a memory array, which generally includes the memory cells coupled to a grid of word lines and bit lines. During formation of the memory device, the memory lines (word lines and bit lines) at the edges of the device are often etched partially or completely, rendering unusable the memory cells to which they are connected. To protect a usable memory cell from damage, the memory device may include, at an edge, a dummy word line (i.e., a word line not used for programming). The dummy word line may not be coupled to a word line driver, thus each memory cell connected to the dummy word line will not be used to store dataxe2x80x94i.e., it is a dummy cell. Consequently, etching of the dummy word line during formation will not result in loss of usable memory.
Conventionally, the dummy word line at the edge is continuously coupled to ground. Thus, regardless of the voltage applied to a corresponding bit line (whether a program or erase voltage), the dummy cell is in a constant state of being weakly erased, which leads to over-erasure of the dummy cell. This over-erasure results in current leakage along the bit lines coupled to the over-erased dummy cells during read operations of usable memory cells.
FIG. 1 demonstrates the relationship between current leakage of a bit line and the threshold voltage of a dummy cell coupled to a dummy word line (xe2x80x9cVTxe2x80x9d) as compared to the number of cycles (i.e., program and erase operations) performed when the dummy word line is coupled to ground. Line 110 represents the current leakage of a bit line coupled to a dummy cell (xe2x80x9cBD leakagexe2x80x9d) in relation to the number of cycles, and line 120 represents the threshold voltage needed to turn on a dummy cell in relation to the number of cycles.
A memory device with the characteristics illustrated in FIG. 1 includes a dummy word line that is set to approximately 0 volts during program and erase operations. During a program operation, the drain voltage applied to the bit line is set to approximately 7 volts, the source voltage is set to approximately 0 volts, the substrate voltage is set to approximately 0 volts, and the voltage is applied for roughly 2 xcexcs. During an erase operation, the drain voltage applied to the bit line is set to approximately 7.5 volts, the source voltage is allowed to float, the substrate voltage is set to approximately 0 volts, and the voltage is applied for roughly 40 ms.
As line 110 illustrates, the initial BD leakage is 0.000782 xcexcA, whereas after 30,000 programming cycles, the BD leakage is 0.281 xcexcA. That is, after 30,000 programming cycles, the current leakage of the bit line coupled to a dummy cell increases by 0.280218 xcexcA. As line 120 illustrates, the initial threshold voltage is 1.131 volts, whereas after 30,000 programming cycles, the threshold voltage decreases by 0.2122 volts to 0.9188 volts.
Further, the semiconductor memory device may be tested, as is commonly done, for leakage by baking it for 4 hours at 150xc2x0 C. after 30,000 cycles. If this is done, the current leakage will be 0.473 xcexcA, for an increase of 0.472218 xcexcA from the initial state, and the threshold voltage will drop to 0.733 volts for a drop of 0.398 volts from the initial state.
What is desired is a system and method that reduces the amount of leakage along the bit line that results from over-erasing a dummy cell while avoiding loss of usable memory cells that may result during formation.
Systems and methods consistent with the present invention satisfy the above need by providing a semiconductor memory device that reduces the current leakage along the bit line by coupling a dummy word line at the edge of a memory device to a positive power source.
In one embodiment consistent with the invention, a semiconductor memory device comprises a memory cell, a dummy word line coupled to the memory cell, a control logic for supplying a positive bias to the dummy word line during an erase operation, and at least one bit line coupled to the memory cell.
In another embodiment consistent with the invention, a semiconductor memory array comprises a memory cell, at least one bit line arranged in a first direction and coupled to the memory cell; and at least one dummy word line arranged in a second direction perpendicular to the at least one bit line and coupled to the memory cell, wherein a positive bias is selectively supplied to the at least one dummy word line at least during erase operation.
Additional features and advantages consistent with the invention will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages consistent with the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.